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56F827 Fiches technique(PDF) 12 Page - Freescale Semiconductor, Inc |
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56F827 Fiches technique(HTML) 12 Page - Freescale Semiconductor, Inc |
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12 / 60 page ![]() 56F827 Technical Data, Rev. 12 12 Freescale Semiconductor A0 (GPIOA0) 21 Output Input/Output Address Bus—A0–A15 specify the address for external Program or Data memory accesses. Port A GPIO—These 16 General Purpose I/O (GPIO) pins can be individually programmed as input or output pins. After reset, the default state is Address Bus. A1 (GPIOA1) 22 A2 (GPIOA2) 23 A3 (GPIOA3) 24 A4 (GPIOA4) 25 A5 (GPIOA5) 26 A6 (GPIOA6) 27 A7 (GPIOA7) 28 A8 (GPIOA8) 31 A9 (GPIOA9) 32 A10 (GPIOA10) 33 A11 (GPIOA11) 34 A12 (GPIOA12) 35 A13 (GPIOA13) 36 A14 (GPIOA14) 37 A15 (GPIOA15) 38 Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued) Signal Name Pin No. Type Description |
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