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ST92163 - INTERRUPTS

INTERRUPTS (Cont’d)

3.2 INTERRUPT VECTORING

The ST9 implements an interrupt vectoring struc-

ture which allows the on-chip peripheral to identify

the location of the first instruction of the Interrupt

Service Routine automatically.

When an interrupt request is acknowledged, the

peripheral interrupt module provides, through its

Interrupt Vector Register (IVR), a vector to point

into the vector table of locations containing the

start addresses of the Interrupt Service Routines

(defined by the programmer).

Each peripheral has a specific IVR mapped within

its Register File pages.

The Interrupt Vector table, containing the address-

es of the Interrupt Service Routines, is located in

the first 256 locations of Memory pointed to by the

ISR register, thus allowing 8-bit vector addressing.

For a description of the ISR register refer to the

chapter describing the MMU.

The user Power on Reset vector is stored in the

first two physical bytes in memory, 000000h and

000001h.

The Top Level Interrupt vector is located at ad-

dresses 0004h and 0005h in the segment pointed

to by the Interrupt Segment Register (ISR).

With one Interrupt Vector register, it is possible to

address several interrupt service routines; in fact,

peripherals can share the same interrupt vector

most significant bits of the vector are user pro-

grammable to define the base vector address with-

in the vector table, the least significant bits are

controlled by the interrupt module, in hardware, to

select the appropriate vector.

Note: The first 256 locations of the memory seg-

ment pointed to by ISR can contain program code.

3.2.1 Divide by Zero trap

The Divide by Zero trap vector is located at ad-

dresses 0002h and 0003h of each code segment;

it should be noted that for each code segment a

Divide by Zero service routine is required.

Warning. Although the Divide by Zero Trap oper-

ates as an interrupt, the FLAG Register is not

pushed onto the system Stack automatically. As a

result it must be regarded as a subroutine, and the

service routine must end with the RET instruction

(not IRET ).

Figure 20. Interrupt Vector Table

USER ISR

PROGRAM MEMORY

POWER-ON RESET

DIVIDE-B Y-ZERO

TOP LEVEL INT.

000000h

USER MAIN PROGRAM

USER TOP LEVEL ISR

USER DIVIDE-BY -ZERO ISR

0000FFh

VECTOR

TABLE

ISR ADDRES S

EVEN

ODD

INT. VECTOR REGIS TER

REGISTE R FILE

R240

R239

F PAGE REGISTE RS

000002h

000004h

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