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ST92163 Fiches technique(PDF) 83 Page - STMicroelectronics |
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ST92163 Fiches technique(HTML) 83 Page - STMicroelectronics |
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83 / 224 page ![]() 83/224 ST92163 - RESET AND CLOCK CONTROL UNIT (RCCU) PLL CONFIGURATION REGISTER (PLLCONF) R246 - Read/Write Register Page: 55 Reset Value: xx00 x111 Bit 7:6 = Reserved. Bit 5:4 = MX[1:0]: PLL Multiplication Factor. Refer to Table 14 for multiplier settings. Bit 3 = Reserved. Bit 2:0 = DX[2:0]: PLL output clock divider factor. Refer to Table 15 for divider settings. Table 14. PLL Multiplication Factors Table 15. Divider Configuration Figure 39. RCCU General Timing 70 - - MX1 MX0 - DX2 DX1 DX0 MX1 MX0 CLOCK2 x 10 14 00 10 11 8 01 6 DX2 DX1 DX0 CK 0 0 0 PLL CLOCK/1 0 0 1 PLL CLOCK/2 0 1 0 PLL CLOCK/3 0 1 1 PLL CLOCK/4 1 0 0 PLL CLOCK/5 1 0 1 PLL CLOCK/6 1 1 0 PLL CLOCK/7 11 1 CLOCK2 (PLL OFF, Reset State) STOP Acknowledged STOP External Multiplier Xtal INTCLK Internal reset clock clock RESET pin PLL selected by user ((N-1)*512+510)xT Xtal(**) PLL Lock-in time PLL Lock-in time 4xTsys Quartz start-up Exit from RESET 510 x TXtal(*) (*) if DIV2 =1 Switch to PLL clock (**) +/- 1 TXtal PLL turned on by user Xtal/2 PLL PLL Xtal/2 |
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