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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ST7261 Fiches technique(PDF) 78 Page - STMicroelectronics |
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ST7261 Fiches technique(HTML) 78 Page - STMicroelectronics |
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78 / 80 page  ERRATA SHEET 78/80 18 SILICON LIMITATIONS 18.1 LVD RESET ON VDD BROWNOUT If VDD drops into the range 2.4V to 0.5V but does not go below 0.5V, the LVD reset is not held low and follows the level of VDD. In this case, USBVCC may not be correctly acti- vated. At power-on, VDD must rise monotonously to ensure the LVD reset stays low until the VIT+ threshold is crossed (see Figure 58) To reset the device correctly and recover normal operation, the VDD must be brought below 0.5V. The LVD reset functions correctly if VDD drops into the range VIT- to 2.4V or if VDD drops below 0.5V. Figure 58. LVD Reset on VDD Brownout VIT- 2.4 0.5 VIT+ RESET UNCORRECT FUNCTION |
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