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5.2 LOW VOLTAGE DETECTOR (LVD)

The on-chip Low Voltage Detector is enabled by

setting a bit in the option bytes (refer to the Option

Bytes section of this document).

The LVD allows the device to be used without any

external RESET circuitry. In this case, the RESET

pin should be left unconnected.

If the LVD is not used, an external circuit is manda-

tory to ensure correct Power On Reset operation,

see figure in the Reset section. For more details,

please refer to the application note AN669.

The LVD generates a static Reset when the supply

voltage is below a reference value. This means

that it secures the power-up as well as the power-

down keeping the ST6 in reset.

The V

IT- reference value for a voltage drop is lower

than the V

IT+ reference value for power-on in order

to avoid a parasitic reset when the MCU starts run-

ning and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when

VDD is below:

– V

IT+ when V

DD is rising

– V

IT- when V

DD is falling

The LVD function is illustrated in Figure 12.

If the LVD is enabled, the MCU can be in only one

of two states:

– Over the input threshold voltage, it is running un-

der full software control

– Below the input threshold voltage, it is in static

safe reset

In these conditions, secure operation is guaran-

teed without the need for external reset hardware.

During a Low Voltage Detector Reset, the RESET

pin is held low, thus permitting the MCU to reset

other devices.

Figure 12. Low Voltage Detector Reset

VDD

VIT+

RESET

VIT-

Vhyst

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