NRF52810-QFAA-R datasheet(326/483 Pages) NORDIC

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Peripherals

SysClk

LFClk

PRESC

COUNTER

CC[0]

COMPARE[0]

0x000

N-2

N-1

N+1

>= 0

Figure 83: Timing diagram - COMPARE_N+1

• If the COUNTER is N and the current CC register value is N+1 or N+2 when a new CC value is written, a

match may trigger on the previous CC value before the new value takes effect. If the current CC value

greater than N+2 when the new value is written, there will be no event due to the old value.

SysClk

LFClk

PRESC

COUNTER

CC[0]

COMPARE[0]

0x000

N-2

N-1

N+1

>= 0

Figure 84: Timing diagram - COMPARE_N-1

6.16.8 TASK and EVENT jitter/delay

Jitter or delay in the RTC is due to the peripheral clock being a low frequency clock (LFCLK) which is not

synchronous to the faster PCLK16M.

Registers in the peripheral interface, part of the PCLK16M domain, have a set of mirrored registers in the

LFCLK domain. For example, the COUNTER value accessible from the CPU is in the PCLK16M domain and

is latched on read from an internal register called COUNTER in the LFCLK domain. COUNTER is the register

which is actually modified each time the RTC ticks. These registers must be synchronised between clock

domains (PCLK16M and LFCLK).

The following is a summary of the jitter introduced on tasks and events. Figures illustrating jitter follow.

Task

Delay

CLEAR, STOP, START, TRIGOVRFLOW

+15 to 46 μs

Table 65: RTC jitter magnitudes on tasks

4430_161 v1.0

326

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