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74LVC86APW Fiches technique(PDF) 7 Page - Nexperia B.V. All rights reserved |
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74LVC86APW Fiches technique(HTML) 7 Page - Nexperia B.V. All rights reserved |
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7 / 15 page ![]() © Nexperia B.V. 2017. All rights reserved 74LVC86A All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 5 — 19 October 2011 7 of 15 Nexperia 74LVC86A Quad 2-input EXCLUSIVE-OR gate 11. AC waveforms VM =1.5 V atVCC 2.7 V VM =0.5 VCC at VCC <2.7 V. VOL and VOH are typical output voltage levels that occur with the output load. Test data is given in Table 8. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 6. The input nA, nB to output nY propagation delays Fig 7. Test circuit for measuring switching times mna244 tPHL tPLH VM VM nA, nB input nY output GND VI VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aaf615 VCC VI VO DUT CL RT RL PULSE GENERATOR Table 8. Test data Supply voltage Input Load VI tr, tf CL RL 1.2 V VCC 2 ns 30 pF 1 k 1.65 V to 1.95 V VCC 2 ns 30 pF 1 k 2.3 V to 2.7 V VCC 2 ns 30 pF 500 2.7V 2.7V 2.5 ns 50 pF 500 3.0Vto 3.6V 2.7V 2.5 ns 50 pF 500 |
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