74LVC86APW datasheet(3/15 Pages) NEXPERIA

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74LVC86A

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Product data sheet

Rev. 5 — 19 October 2011

3 of 15

Nexperia

74LVC86A

Quad 2-input EXCLUSIVE-OR gate

Pinning information

5.1 Pinning

5.2 Pin description

Functional description

[1]

H = HIGH voltage level; L = LOW voltage level

(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to GND.

Fig 4.

Pin configuration for SO14 and (T)SSOP14

Fig 5.

Pin configuration for DHVQFN14

VCC

GND

001aad103

001aad105

Transparent top view

GND(1)

terminal 1

index area

Table 2.

Pin description

Symbol

Description

1A, 2A, 3A, 4A

1, 4, 9, 12

data input

1B, 2B, 3B, 4B

2, 5, 10, 13

data input

1Y, 2Y, 3Y, 4Y

3, 6, 8, 11

data output

GND

ground (0 V)

VCC

supply voltage

Table 3.

Functional table[1]

Input

Output

LLL

HHL

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