Data Sheet

AD5273

Rev. J | Page 7 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

W

Wiper Terminal W. GND ≤ V

W ≤ VDD.

2

V

DD

Positive Power Supply. Specified for non-OTP operation from 2.7 V to 5.5 V. For OTP programming, V

DD_OTP

must be set within the window of 5 V to 5.5 V for all end to end resistance options, and be capable of sourcing

100 mA.

3

GND

Common Ground.

4

SCL

Serial Clock Input. Requires a pull-up resistor. If it is driven directly from a logic controller without the pull-up

resistor, ensure that the V

IH minimum is 0.7 × VDD.

5

SDA

Serial Data Input/Output. Requires a pull-up resistor. If it is driven directly from a logic controller without the

pull-up resistor, ensure that the V

IH minimum is 0.7 × VDD.

6

AD0

I2C Device Address Bit. Allows a maximum of two AD5273 devices to be addressed.

7

B

Resistor Terminal B. GND ≤ V

B ≤ VDD.

8

A

Resistor Terminal A. GND ≤ V

A ≤ VDD.

W

1

VDD 2

GND

3

SCL

4

A

8

B

7

AD0

6

SDA

5

AD5273

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