AD5273BRJZ1-R2 datasheet(19/20 Pages) AD

19 / 20 page

Data Sheet

AD5273

Rev. J | Page 19 of 20

Depending on the op amp GBP, reducing the feedback resistor

may extend the zero’s frequency far enough to overcome the

problem. A better approach is to include a compensation

capacitor, C2, to cancel the effect caused by C1. Optimum

compensation occurs when R1 × C1 = R2 × C2, but this is not

an option because of the variation of R2. As a result, users can

use the relationship described and scale C2 as if R2 were at its

maximum value. However, doing so may overcompensate by

slowing down the settling time when R2 is set to low values. To

avoid this problem, C2 should be found empirically for a given

application. In general, setting C2 in the range of a few picofarads

to no more than a few tenths of a picofarad is usually adequate

for compensation.

There is also a Terminal W capacitance connected to the output

(not shown); its effect on stability is less significant; therefore,

compensation is not necessary unless the op amp is driving a

large capacitive load.

PROGRAMMABLE LOW-PASS FILTER

In ADC applications, it is common to include an antialiasing

filter to band-limit the sampling signal. To minimize various

system redesigns, users can use two 1 kΩ AD5273s to construct

a generic second-order Sallen-Key low-pass filter. Because the

AD5273 is a single-supply device, the input must be dc offset

when an ac signal is applied to avoid clipping at ground. This is

illustrated in Figure 47. The design equations are

(6)

1R2C1C2

(7)

R2C2

R1C1

1 +

(8)

Users can first select some convenient values for the capacitors.

To achieve maximally flat bandwidth where Q = 0.707, let C1 be

twice the size of C2 and let R1 = R2. As a result, R1 and R2 can

be adjusted to the same setting to achieve the desired bandwidth.

Figure 47. Sallen Key Low-Pass Filter

LEVEL SHIFT FOR DIFFERENT VOLTAGES

OPERATION

If the SCL and SDA signals come from a low voltage logic

controller and are below the minimum VIH level (0.7 × VDD),

level-shift the signals for successful read/write communication

between the AD5273 and the controller. Figure 48 shows one of

the implementations. For example, when SDA1 is 2.5 V, M1

turns off, and SDA2 becomes 5 V. When SDA1 is 0 V, M1 turns

on, and SDA2 approaches 0 V. As a result, proper level-shifting

is established. M1 and M2 should be low threshold N-Channel

power MOSFETs, such as FDV301N.

Figure 48. Level Shift for Different Voltages Operation

RDAC CIRCUIT SIMULATION MODEL

The internal parasitic capacitances and the external capacitive

loads dominate the ac characteristics of the digital potentio-

meters. Configured as a potentiometer divider, the −3 dB

bandwidth of the AD5273 (1 kΩ resistor) measures 6 MHz at

half scale. Figure 17 to Figure 20 provide the large signal BODE

plot characteristics of the four available resistor versions: 1 kΩ,

10 kΩ, 50 kΩ, and 100 kΩ. Figure 49 shows a parasitic simula-

tion model. The code following Figure 49 provides a macro

model net list for the 1 kΩ device.

Figure 49. Circuit Simulation Model for RDAC = 1 kΩ

Macro Model Net List for RDAC

.PARAM D = 63, RDAC = 1E3

.SUBCKT DPOT (A,W,B)

CA A 0 25E-12

RWA A W {(1-D/63)*RDAC+60}

CW W 0 55E-12

RWB W B {D/63*RDAC+60}

CB B 0 25E-12

.ENDS DPOT

AD8601

+2.5V

–2.5V

V+

V–

W C2

ADJUSTED TO

SAME SETTINGS

2.5V

CONTROLLER

2.7V–5.5V

AD5273

VDD1 = 2.5V

VDD2 = 5V

SDA1

SCL1

SDA2

SCL2

55pF

25pF

Ω

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