AD5273BRJZ1-R2 datasheet(16/20 Pages) AD

16 / 20 page

AD5273

Data Sheet

Rev. J | Page 16 of 20

CONTROLLING THE AD5273

I2C CONTROLLER PROGRAMMING

Write Bit Patterns

Figure 39. Writing to the RDAC Register

Figure 40. Activating One-Time Programming

Read Bit Pattern

Figure 41. Reading Data from the RDAC Register

For users who do not use the software solution, the AD5273 can

be controlled via an I2C-compatible serial bus and is connected

to this bus as a slave device. Referring to Figure 39, Figure 40,

and Figure 41, the 2-wire I2C serial bus protocol operates as

follows:

1. The master initiates data transfer by establishing a start

condition. A start condition is defined as a high-to-low

transition on the SDA line while SCL is high, as shown in

Figure 39. The byte following the start condition is the

slave address byte, which consists of six MSBs defined as

010110. The next bit is AD0; it is an I2C device address bit.

Depending on the states of the AD0 bits, two AD5273s can

be addressed on the same bus, as shown in Figure 42. The

last LSB is the R/W bit, which determines whether data is

read from or written to the slave device.

The slave address corresponding to the transmitted address

responds by pulling the SDA line low during the ninth

clock pulse (this is termed the acknowledge bit). At this

stage, all other devices on the bus remain idle while the

selected device waits for data to be written to or read from

its serial register.

2. A write operation contains one more instruction byte than

the read operation. The instruction byte in the write mode

follows the slave address byte. The MSB of the instruction

byte labeled T is the OTP bit. After acknowledging the

instruction byte, the last byte in the write mode is the data

byte. Data is transmitted over the serial bus in sequences of

nine clock pulses (eight data bits followed by an acknowl-

edge bit). The transitions on the SDA line must occur during

the low period of SCL and remain stable during the high

period of SCL, as shown in Figure 39.

3. In read mode, the data byte follows immediately after the

acknowledgment of the slave address byte. Data is trans-

mitted over the serial bus in sequences of nine clock pulses

(slight difference from write mode, there are eight data bits

followed by a no acknowledge bit). Similarly, the transitions

on the SDA line must occur during the low period of SCL

and remain stable during the high period of SCL, as shown

in Figure 41.

ACK. BY

AD5273

ACK. BY

AD5273

ACK. BY

AD5273

SDA

FRAME 1

SLAVE ADDRESS BYTE

SCL

STOP BY

MASTER

START BY

MASTER

AD0 R/W

FRAME 2

INSTRUCTION BYTE

FRAME 1

DATA BYTE

ACK. BY

AD5273

ACK. BY

AD5273

ACK. BY

AD5273

FRAME 1

SLAVE ADDRESS BYTE

STOP BY

MASTER

START BY

MASTER

FRAME 2

INSTRUCTION BYTE

FRAME 1

DATA BYTE

SDA

SCL

AD0 R/W

ACK. BY

AD5273

NO ACK. BY

AD5273

FRAME 1

SLAVE ADDRESS BYTE

STOP BY

MASTER

START BY

MASTER

FRAME 2

DATA BYTE FROM SELECTED

RDAC REGISTER

SDA

SCL

AD0 R/W

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