ST7L09 datasheet(89/104 Pages) STMICROELECTRONICS

89 / 104 page

ST7L05, ST7L09

89/104

13.10

COMMUNICATION

INTERFACE

CHARACTERISTICS

13.10.1 SPI - Serial Peripheral Interface

Subject to general operating conditions for VDD,

fOSC and TA, unless otherwise specified.

Refer to I/O port characteristics for more details on

the input/output alternate function characteristics

(SS, SCK, MOSI, MISO).

Figure 65. SPI Slave Timing Diagram with CPHA = 03)

Notes:

1. Data based on design simulation and/or characterization results, not tested in production.

2. When no communication is on-going, the data output line of the SPI (MOSI in master mode, MISO in slave mode) has

its alternate function capability released. In this case, the pin status depends on the I/O port configuration.

3. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD.

Symbol

Parameter

Conditions

Min

Max

Unit

fSCK =1/tc(SCK) SPI clock frequency

Master (fCPU = 8 MHz)

fCPU/128 = 0.0625 fCPU/4 = 2

MHz

Slave (fCPU = 8 MHz)

fCPU/2 = 4

tr(SCK)

tf(SCK)

SPI clock rise and fall time

see I/O port pin description

tsu(SS)

SS setup time

Slave

120

th(SS)

SS hold time

tw(SCKH)

tw(SCKL)

SCK high and low time

Master

Slave

100

tsu(MI)

tsu(SI)

Data input setup time

Master

Slave

100

th(MI)

th(SI)

Data input hold time

Master

Slave

100

ta(SO)

Data output access time

Slave

120

tdis(SO)

Data output disable time

Slave

240

tv(SO)

Data output valid time

Slave (after enable edge)

120

th(SO)

Data output hold time

tv(MO)

Data output valid time

Master (after enable edge)

120

th(MO)

Data output hold time

SS INPUT

CPHA = 0

MOSI INPUT

MISO OUTPUT

CPHA = 0

tc(SCK)

tw(SCKH)

tw(SCKL)

tr(SCK)

tf(SCK)

tv(SO)

ta(SO)

tsu(SI)

th(SI)

MSB OUT

MSB IN

BIT6 OUT

LSB IN

LSB OUT

Seenote2

CPOL = 0

CPOL = 1

tsu(SS)

th(SS)

tdis(SO)

th(SO)

See

note 2

BIT1 IN

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