LLCC68 datasheet(49/111 Pages) SEMTECH

49 / 111 page

LLCC68

Data Sheet

Rev. 1.1

DS.LLCC68.W.APP

Dec 2024

49 of 111

Semtech

LLCC68

www.semtech.com

All timings in the following table are given for a maximum load cap of 10pF.

8.2.2 SPI Timing When the Transceiver Leaves Sleep Mode

One way for the chip to leave Sleep mode is to wait for a falling edge of NSS. At falling edge, all necessary internal regulators are switched

On; the chip starts chip initialization before being able to accept first SPI command. This means that the delay between the falling edge of

NSS and the first rising edge of SCK must take into account the wake-up sequence and the chip initialization. In Sleep mode and during the

initialization phase, the busy signal mapped on BUSY pin, is set high indicating to the host that the chip is not able to accept a new command.

Once the chip is in STDBY_RC mode, the busy signal goes low and the host can start sending a command. This is also true for startup at

battery insertion or after a hard reset.

Figure 8-2: SPI Timing Transition

Table 8-1: SPI Timing Requirements

Symbol

Description

Minimum

Typical

Maximum

Unit

NSS falling edge to SCK setup time

SCK period

62.5

SCK high time

31.25

MOSI to SCK hold time

MOSI to SCK setup time

NSS falling to MISO delay

SCK falling to MISO delay,

SCK to NSS rising edge hold time

31.25

NSS high time

125

t10

NSS falling edge to SCK setup time when switching

from SLEEP to STDBY_RC mode

100



t11

NSS falling to MISO delay when switching from

SLEEP to STDBY_RC mode

150



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