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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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XIO2001IPNP Fiches technique(PDF) 58 Page - Texas Instruments |
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XIO2001IPNP Fiches technique(HTML) 58 Page - Texas Instruments |
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58 / 145 page  Table 8-27. Bridge Control Register Description (continued) BIT FIELD NAME ACCESS DESCRIPTION 0 PERR_EN RW Parity error response enable. Controls the bridge's response to data, uncorrectable address, and attribute errors on the secondary interface. Also, the bridge always forwards data with poisoning, from conventional PCI to PCI Express on an uncorrectable conventional PCI data error, regardless of the setting of this bit. 0 = Ignore uncorrectable address, attribute, and data errors on the secondary interface (default) 1 = Enable uncorrectable address, attribute, and data error detection and reporting on the secondary interface XIO2001 SCPS212J – MAY 2009 – REVISED JANUARY 2021 www.ti.com 58 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: XIO2001 |
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