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XIO2001IPNP Fiches technique(PDF) 37 Page - Texas Instruments

No de pièce XIO2001IPNP
Description  XIO2001 PCI Express to PCI Bus Translation Bridge
PDF  145 Pages
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Fabricant  TI2 [Texas Instruments]
Site Internet  https://www.ti.com
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XIO2001IPNP Fiches technique(HTML) 37 Page - Texas Instruments

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SCL From
Master
1
2
3
7
8
9
SDA Output
By Transmitter
SDA Output
By Receiver
Figure 8-11. Serial-Bus Protocol Acknowledge
The bridge performs three basic serial-bus operations: single byte reads, single byte writes, and multibyte reads.
The single byte operations occur under software control. The multibyte read operations are performed by the
serial EEPROM initialization circuitry immediately after a PCI Express reset. See Section 8.3.8.3, Serial-Bus
EEPROM Application, for details on how the bridge automatically loads the subsystem identification and other
register defaults from the serial-bus EEPROM.
Figure 8-12 illustrates a single byte write. The bridge issues a start condition and sends the 7-bit slave device
address and the R/W command bit is equal to 0b. A 0b in the R/W command bit indicates that the data transfer
is a write. The slave device acknowledges if it recognizes the slave address. If no acknowledgment is received
by the bridge, then bit 1 (SB_ERR) is set in the serial-bus control and status register (PCI offset B3h, see
Section 8.4.59). Next, the EEPROM word address is sent by the bridge, and another slave acknowledgment is
expected. Then the bridge delivers the data byte MSB first and expects a final acknowledgment before issuing
the stop condition.
Figure 8-12. Serial-Bus Protocol – Byte Write
Figure 8-13 illustrates a single byte read. The bridge issues a start condition and sends the 7-bit slave device
address and the R/ W command bit is equal to 0b (write). The slave device acknowledges if it recognizes the
slave address. Next, the EEPROM word address is sent by the bridge, and another slave acknowledgment is
expected. Then, the bridge issues a restart condition followed by the 7-bit slave address and the R/ W command
bit is equal to 1b (read). Once again, the slave device responds with an acknowledge. Next, the slave device
sends the 8-bit data byte, MSB first. Since this is a 1-byte read, the bridge responds with no acknowledge (logic
high) indicating the last data byte. Finally, the bridge issues a stop condition.
Figure 8-13. Serial-Bus Protocol – Byte Read
www.ti.com
XIO2001
SCPS212J – MAY 2009 – REVISED JANUARY 2021
Copyright © 2021 Texas Instruments Incorporated
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