IS25LE512M-RGLA3:P-TY datasheet(95/189 Pages) ISSI

No de pièce	IS25LE512M-RGLA3:P-TY

Description	SERIAL FLASH MEMORY 133/112MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

PDF	189 Pages

Scroll/Zoom	100%

Fabricant	ISSI [Integrated Silicon Solution, Inc]

Site Internet	http://www.issi.com

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IS25LE512M

IS25WE512M

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A6

06/16/2025

8.16 WRITE ENABLE OPERATION (WREN, 06h)

The Write Enable (WREN) instruction is used to set the Write Enable Latch (WEL) bit. The WEL bit is reset to the

write-protected state after power-up. The WEL bit must be write enabled before any write operation, including

Sector Erase, Block Erase, Chip Erase, Page Program, Program Information Row, Write Status Register, Write

Function Register, Set Non-Volatile Read Register, Set Non-Volatile Extended Read Register operations, Set

Volatile Read Register and Set Volatile Extended Read Register. The WEL bit will be reset to the write-protected

state automatically upon completion of a write operation. The WREN instruction is required before any above

operation is executed.

Figure 8.41 Write Enable Sequence In SPI Mode

Instruction = 06h

CE#

SCK

Mode 3

Mode 0

High Impedance

Figure 8.42 Write Enable Sequence In QPI Mode

06h

CE#

SCK

IO[3:0]

Mode 3

Mode 0

IS25LE512M-RGLA3:P-TY Fiches technique(PDF) 95 Page - Integrated Silicon Solution, Inc