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L9347 Fiches technique(PDF) 15 Page - STMicroelectronics |
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L9347 Fiches technique(HTML) 15 Page - STMicroelectronics |
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15 / 29 page ![]() L9347 Functional Description 15/29 The output current is measured during the recirculation of the load. The current sense resistor is in series to the free wheeling diode. If this recirculation path is interrupted the regulator stops immediately and the status output remains low for the rest of the input cycle. The output period is 64 times the clock period. With a clock frequency of 250kHz the output PWM frequency is 3.9kHz. The output PWM is synchronized with the first negative edge of the input signal. After that the output and the input are asynchronous. The first period is used to measure the current. This means the first turn-on of the power is 256 s after the first negative edge of the input signal. As regulator a digital PI-regulator with the Transfer function for: KI: and KP: 0.96 for a sampling time of 256 s is realised. To speed up the current settling time the regulator output is locked to 90% output PWM untill the target current value is reached. This happens alsowhen the target current value changes and the output PWM reaches 90% during the regulation. The status output gets low if the target current value is not reached within the regulation error delay time of tRE=10ms. The output PWM is than out of the regulation range from 10% to 90%. 3.5 Protective circuits The outputs are protected against current overload, overtemperature, and power-GND-loss. The external clock is monitored by a clock watchdog. This clock watchdog detects a minimal frequency f CLK,min and wrong clock duty cycles. The allowed clock duty cycle range is 45% to 55%. The current-regulator stages are protected against recirculation errors, when D3 or D4 is not connected. All these error conditions shut off the power stage and invert the status output information. 3.6 Error detection The status outputs indicate the switching state under normal conditions (status LOW = OFF; status HIGH = ON). If an error occurs, the logic level of the status output is inverted, as listed in the diagnostic table below. All external errors, for example open load, are filtered internally. The following table shows the detected errors, the filter times and the detection mode (on/off). 0.126 z1 – --------------- |
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