| Moteur de recherche de fiches techniques de composants électroniques |
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L9300 Fiches technique(PDF) 80 Page - STMicroelectronics |
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L9300 Fiches technique(HTML) 80 Page - STMicroelectronics |
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80 / 178 page ![]() Figure 49. Reset-Latch timing diagram VBATP POR WAKE Reset due to WD_fault RES1 Clear Clear RES1_LATCH signal is forced “high” by 4 count of WD_fault generation Clear Clear Clear Clear Clear Clear WD_fault-counter RES1/LATCH GADG0408171001PS 13.2 PRUN watchdog electrical characteristics 5.5V ≤ VBATP ≤ 19V; -40°C ≤ Tj ≤ 175°C unless otherwise noticed. All voltages refer to GND pin. Table 50. PRUN WD electrical characteristics Symbol Parameter Test condition Min Typ Max Unit Pin Input Pin Vil(PRN) Low Input Voltage - 0.75 V PRN Vih(PRN) High Input Voltage 1.75 V PRN Ipd(PRN) Pull-down Input Current PRN = 5 V 10 50 100 µA PRN Vil(WD_DIS) Low Input Voltage 0.75 V WD_DIS Vih(WD_DIS) High Input Voltage 1.75 V WD_DIS Ipd(WD_DIS) Pull-down Input Current WD_DIS = 5 V 10 50 100 µA WD_DIS PRUN Timings Toff_to Timeout at power up Guaranteed by scan 230 300 370 ms PRN Toff Clock off reset time Guaranteed by scan 11 16 ms PRN TRL Reset pulse low time Guaranteed by scan 1 1.25 ms RES1 TRH Reset pulse high time Guaranteed by scan 230 300 370 ms RES1 FreqH PRUN Over Frequency Detection Guaranteed by scan 1 kHz PRN L9300 PRUN watchdog DS12258 - Rev 5 page 80/178 |
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