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L9800 Fiches technique(PDF) 24 Page - STMicroelectronics |
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L9800 Fiches technique(HTML) 24 Page - STMicroelectronics |
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24 / 55 page ![]() Figure 18. Scenario 5 power-down VBATT VDDIO IN0 POR t V V3V3 V1V2 Scenario 5: power-down with VBATT ping down after VDDIO. When even VBATT undergoes 2 V, although IN0 is still high, internal supply reference and vbg ; POR is set to zero. IDLE = IN1 = 0 V. Figure 19. Scenario 6 power-down VBATT VDDIO IN0 POR t V V3V3 V1V2 Scenario 6: power-down with VDDIO ping down after VBATT. When even VDDIO undergoes 3 V, although IN0 is still high, internal supply reference and vbg ; POR is set to zero, IDLE = IN1 = 0 V. As for scenario 5, the same condition happens if, instead of IN0, one of the other pins is high or two of them or all of them. L9800 Power supply DS14041 - Rev 2 page 24/55 |
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