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PUSB3AB4

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Product data sheet

Rev. 2 — 4 May 2016

7 of 13

Nexperia

PUSB3AB4

ESD protection for ultra high-speed interfaces

The device uses an advanced clamping structure showing a negative dynamic resistance.

This snapback behavior strongly reduces the clamping voltage to the system behind the

ESD protection during an ESD event. Do not connect unlimited DC current sources to the

data lines to avoid keeping the ESD protection device in snapback state after exceeding

breakdown voltage (due to an ESD pulse for instance).

Transmission Line Pulse (TLP) = 100 ns

Transmission Line Pulse (TLP) = 100 ns

Fig 9.

Dynamic resistance with positive clamping;

typical values

Fig 10. Dynamic resistance with negative clamping;

typical values

Very-Fast Transmission Line Pulse (VF-TLP) = 5 ns

Very-Fast Transmission Line Pulse (VF-TLP) = 5 ns

Fig 11. Dynamic resistance with positive clamping;

typical values

Fig 12. Dynamic resistance with negative clamping;

typical values

VCL (V)

030

20

10

aaa-023072

10

20

30

IPP

(A)

0

VCL (V)

-30

0

-10

-20

aaa-023073

-20

-10

0

IPP

(A)

-30

VCL (V)

030

20

10

aaa-023074

10

20

30

IPP

(A)

0

VCL (V)

-30

0

-10

-20

aaa-023075

-20

-10

0

IPP

(A)

-30