ADS7828-Q1

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SBAS456B – DECEMBER 2008 – REVISED JANUARY 2016

Switching Characteristics (continued)

+VDD = 2.7 V, over operating free-air temperature range, unless otherwise noted.

(1)(2) See Figure 1.

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Standard mode

4

μs

Fast mode

600

thigh

High period of the SCL clock

Cb = 100 pF max

60

ns

High-speed mode(3)

Cb = 400 pF max

120

Standard mode

4.7

μs

Setup time for a repeated Start

tSU; STA

Fast mode

600

condition

ns

High-speed mode

160

Standard mode

250

tSU; DAT

Data setup time

Fast mode

100

ns

High-speed mode

10

Standard mode

0

3.45

μs

Fast mode

0

0.9

tHD; DAT

Data hold time

Cb = 100 pF max

0

82

High-speed mode(3) (4)

ns

Cb = 400 pF max

0

162

Standard mode

1000

Fast mode

20 + 0.1Cb

300

trCL

Rise time of SCL signal

ns

Cb = 100 pF max

10

40

High-speed mode(3)

Cb = 400 pF max

20

80

Standard mode

1000

Rise time of SCL signal after a

Fast mode

20 + 0.1Cb

300

trCL1

repeated Start condition and after an

ns

Cb = 100 pF max

10

80

acknowledge bit

High-speed mode(3)

Cb = 400 pF max

20

160

Standard mode

300

Fast mode

20 + 0.1Cb

300

tfCL

Fall time of SCL signal

ns

Cb = 100 pF max

10

40

High-speed mode(3)

Cb = 400 pF max

20

80

Standard mode

1000

Fast mode

20 + 0.1Cb

300

trDA

Rise time of SDA signal

ns

Cb = 100 pF max

10

80

High-speed mode(3)

Cb = 400 pF max

20

160

Standard mode

300

Fast mode

20 + 0.1Cb

300

tfDA

Fall time of SDA signal

ns

Cb = 100 pF max

10

80

High-speed mode(3)

Cb = 400 pF max

20

160

Standard mode

4

μs

tSU; STO

Setup time for Stop condition

Fast mode

600

ns

High-speed mode

160

Cb

Capacitive load for SDA or SCL

400

pF

Fast mode

50

tSP

Pulse width of spike suppressed

ns

High-speed mode

10

Noise margin at the high level for

VnH

each connected device (including

0.2 × VDD

V

hysteresis)

Noise margin at the low level for

VnL

each connected device (including

0.1 × VDD

V

hysteresis)

(4)

A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH

signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.

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