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STR910FAM32H6T Fiches technique(PDF) 62 Page - STMicroelectronics |
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STR910FAM32H6T Fiches technique(HTML) 62 Page - STMicroelectronics |
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62 / 99 page ![]() Electrical characteristics STR91xFAx32 STR91xFAx42 STR91xFAx44 62/99 7.5.1 LVD delay timing Case 1: When VDDQ reaches the VDDQ_LVD+ threshold after the first ~10 ms delay (introduced by the VDD rising edge), a new ~10 ms delay starts before the release of RESET_OUTn. See Figure 12. Figure 12. LVD reset delay case 1 Case 2: When VDDQ reaches the VDDQ_LVD+ threshold before the first ~10 ms delay (introduced by the VDD rising edge), RESET_OUTn will be released immediately at the end of the delay. No new delay is introduced in this case. See Figure 13. Figure 13. LVD reset delay case 2 Case 3: When VDD reaches the VDD_LVD+ threshold after the VDDQ rising edge, RESET_OUTn will be released at the end of a ~10 ms delay. See Figure 14 Figure 14. LVD reset delay case 3 VDD_LVD+ VDDQ_LVD+ ~10 ms delay ~10 ms delay VDDQ (red) RESET_OUTn (blue) VDD (green) VDD_LVD+ VDDQ_LVD+ ~10 ms delay VDDQ (red) RESET_OUTn (blue) VDD (green) VDD_LVD+ VDDQ_LVD+ ~10 ms delay VDDQ (red) RESET_OUTn (blue) VDD (green) |
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