M25PE16-VMP6TP datasheet(49/56 Pages) STMICROELECTRONICS

49 / 56 page

M25PE16

DC and AC parameters

49/56

Table 18.

AC characteristics

Test conditions specified in

Table 14 and Table 15

Symbol

Alt.

Parameter

Min.

Typ.

Max.

Unit

Clock Frequency for the following instructions:

FAST_READ, RDLR, PW, PP, WRLR, PE, SE,

SSE, DP, RDP, WREN, WRDI, RDSR, WRSR

D.C.

MHz

Clock Frequency for READ instructions

D.C.

MHz

tCH

(1)

tCLH Clock High Time

tCL

(1)

tCLL

Clock Low Time

Clock Slew Rate 2 (peak to peak)

0.1

V/ns

tSLCH

tCSS S Active Setup Time (relative to C)

tCHSL

S Not Active Hold Time (relative to C)

tDVCH

tDSU Data In Setup Time

tCHDX

tDH

Data In Hold Time

tCHSH

S Active Hold Time (relative to C)

tSHCH

S Not Active Setup Time (relative to C)

tSHSL

tCSH S Deselect Time

100

tSHQZ

(2)

tDIS

Output Disable Time

tCLQV

Clock Low to Output Valid

tCLQX

tHO

Output Hold Time

tWHSL

(3)

Write Protect Setup Time

tSHWL

(3)

Write Protect Hold Time

100

tDP

(2)

S to Deep Power-down

µs

tRDP

(2)

S High to Standby Mode

µs

Write Status Register Cycle Time

tPW

(4)

Page Write Cycle Time (256 Bytes)

tPP

(4)

Page Program Cycle Time (256 Bytes)

0.8

3ms

Page Program Cycle Time (n Bytes)

int(n/8) × 0.025(5)

tPE

Page Erase Cycle Time

tSE

Sector Erase Cycle Time

tSSE

SubSector Erase Cycle Time

150

tBE

Bulk Erase Cycle Time

tCH + tCL must be greater than or equal to 1/ fC

Value guaranteed by characterization, not 100% tested in production.

Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

When using PP and PW instructions to update consecutive Bytes, optimized timings are obtained with one sequence

including all the Bytes versus several sequences of only a few Bytes (1

≤n ≤256).

int(A) corresponds to the upper integer part of A. E.g. int(12/8) = 2, int(32/8) = 4 int(15.3) =16.

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