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M25PE16-VMP6TP Fiches technique(PDF) 7 Page - STMicroelectronics |
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M25PE16-VMP6TP Fiches technique(HTML) 7 Page - STMicroelectronics |
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7 / 56 page ![]() M25PE16 Description 7/56 Figure 1. Logic diagram Figure 2. VFQFPN and SO connections 1. There is an exposed die paddle on the underside of the MLP8 package. This is pulled, internally, to VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB. 2. See Section 12: Package mechanical for package dimensions, and how to identify pin-1. Table 1. Signal names C Serial Clock D Serial Data Input Q Serial Data Output S Chip Select W Write Protect RESET Reset VCC Supply Voltage VSS Ground RESET AI12343c S VCC M25PE16 VSS Q C D W 1 AI12344c 2 3 4 8 7 6 5 D VSS C RESET Q SVCC M25PE16 W |
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