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DSP56721 Fiches technique(PDF) 24 Page - Freescale Semiconductor, Inc

No de pièce DSP56721
Description  SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
PDF  54 Pages
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Fabricant  FREESCALE [Freescale Semiconductor, Inc]
Site Internet  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

DSP56721 Fiches technique(HTML) 24 Page - Freescale Semiconductor, Inc

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SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
24
Figure 18. SPI Slave Timing Diagram (CPHA = 1)
2.2.2
Serial Host Interface (SHI) I2C Protocol Timing
See Table 12 for SHI I2C protocol timing parameters and Figure 19 for the timing diagram.
Table 12. SHI I2C Protocol Timing Parameters
Standard I2C
No.
Characteristics1,2,3,4,5
Symbol/
Expression
Standard
Fast-Mode
Unit
Min
Max
Min
Max
Tolerable Spike Width on SCL or SDA
Filters Bypassed
Very Narrow Filters enabled
Narrow Filters enabled
Wide Filters enabled.
–
–
–
–
–
0
10
50
100
–
–
–
–
0
10
50
100
ns
ns
ns
ns
44
SCL clock frequency
FSCL
–
100
–
400
kHz
44
SCL clock cycle
TSCL
10
–
2.5
–
μs
45
Bus free time
TBUF
4.7
–
1.3
–
μs
46
Start condition set-up time
TSUSTA
4.7
–
0.6
–
μs
SS
(Input)
SCK (CPOL = 0)
(Input)
SCK (CPOL = 1)
(Input)
MISO
(Output)
MOSI
(Input)
HREQ
(Output)
23
24
25
26
26
26
26
25
24
31
33
29
30
37
34
32
29
28
27
33
30
36
MSB
LSB
MSB
Valid
LSB
Valid



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