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ADPL40502ACPZ-3.3-R7 Fiches technique(PDF) 7 Page - Analog Devices

No de pièce ADPL40502ACPZ-3.3-R7
Description  Low Noise, 200mA, CMOS Linear Regulator
PDF  17 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

ADPL40502ACPZ-3.3-R7 Fiches technique(HTML) 7 Page - Analog Devices

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Data Sheet
ADPL40502
analog.com
Rev. 0
7 of 17
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. 5-Lead TSOT Pin Configuration
Figure 4. 6-Lead LFCSP Pin Configuration
Pin Descriptions
Table 5. Pin Descriptions
PIN
Mnemonic
DESCRIPTION
TSOT
LFCSP
1
6
VIN
Regulator Input Supply. Bypass VIN to GND with a 1µF or greater
capacitor.
2
3
GND
Ground.
3
4
EN
Enable Input. Drive EN high to turn on the regulator and drive EN low to
turn off the regulator. For automatic startup, connect EN to VIN.
4
2
NC
No Connect. Not connected internally.
5
1
VOUT
Regulated Output Voltage. Bypass VOUT to GND with a 1µF or greater
capacitor.
Not
applicable
5
NC
No Connect. Not connected internally.
Not
applicable
EPAD
Exposed Pad. The exposed pad must be connected to ground. The
exposed pad enhances the thermal performance of the package.
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND.
3
GND
1
VOUT
2
NC
4 EN
6 VIN
5 NC
EPAD
ADPL40502



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