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ADPL40502ACPZ-3.3-R7 Fiches technique(PDF) 3 Page - Analog Devices

No de pièce ADPL40502ACPZ-3.3-R7
Description  Low Noise, 200mA, CMOS Linear Regulator
PDF  17 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

ADPL40502ACPZ-3.3-R7 Fiches technique(HTML) 3 Page - Analog Devices

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Data Sheet
ADPL40502
analog.com
Rev. 0
3 of 17
SPECIFICATIONS
Table 1. Electrical Characteristics
(VIN = (VOUT + 0.4 V) or 2.2 V, whichever is greater, VEN = VIN, IOUT = 10mA, CIN = COUT = 1µF, and TA = -40°C to +125°C (Typ
values at 25°C), unless otherwise noted. Note that VIN is the input voltage, VOUT is the output voltage, IOUT is the
output current, CIN is the input capacitance, and COUT is the output capacitance.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Voltage Range
VIN
2.2
5.5
V
Operating Supply Current
IGND
IOUT = 0µA
20
40
µA
IOUT = 10mA
75
105
µA
IOUT = 200mA
290
390
µA
Shutdown Current
IGND-SD
EN = GND
0.2
1.0
µA
Output Voltage Accuracy
VOUT
IOUT = 10mA
−1
+1
%
100µA < IOUT < 200mA,
VIN = (VOUT + 0.4V) to 5.5V
−3
+2
%
Line Regulation
∆VOUT /∆VIN
VIN = (VOUT + 0.4V) to 5.5V,
TJ = −40°C to +125°C
−0.05
+0.05
%/V
Load Regulation1
∆VOUT /∆IOUT
IOUT = 100µA to 200mA
0.006
0.012
%/mA
Dropout Voltage2
VDROPOUT
IOUT = 10mA
10
30
mV
IOUT = 200mA
150
230
mV
Start-up Time3
tSTART-UP
VOUT = 3.3V
180
µs
Current-Limit Threshold4
ILIMIT
TJ = 0°C to +125°C
220
300
400
mA
Undervoltage Lockout
Input Voltage Rising
UVLORISE
1.96
V
Input Voltage Falling
UVLOFALL
1.28
V
Hysteresis
UVLOHYS
120
mV
Thermal Shutdown
Threshold
TSSD
TJ rising
150
°C
Hysteresis
TSSD-HYS
15
°C
EN Input
Logic High
VIH
2.2V ≤ VIN ≤ 5.5V
1.2
V
Logic Low
VIL
2.2V ≤ VIN ≤ 5.5V
0.4
V
Pull-Down Resistance
REN
VIN = EN voltage (VEN) = 5.5V
2.6
Output Noise



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