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UPSD3422EB40U6 Fiches technique(PDF) 140 Page - STMicroelectronics |
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UPSD3422EB40U6 Fiches technique(HTML) 140 Page - STMicroelectronics |
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140 / 293 page ![]() SPI (synchronous peripheral interface) uPSD34xx 140/293 Table 63. SPICON0: control register 0 (SFR D6h, reset value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – TE RE SPIEN SSEL FLSB SBO – Bit Symbol R/W Definition 7 – – Reserved 6TE RW Transmitter Enable 0 = Transmitter is disabled 1 = Transmitter is enabled 5RE RW Receiver Enable 0 = Receiver is disabled 1 = Receiver is enabled 4 SPIEN RW SPI Enable 0 = Entire SPI Interface is disabled 1 = Entire SPI Interface is enabled 3SSEL RW Slave Selection 0 = SPISEL output pin is constant logic '1' (slave device not selected) 1 = SPISEL output pin is logic '0' (slave device is selected) during data transfers 2FLSB RW First LSB 0 = Transfer the most significant bit (MSB) first 1 = Transfer the least significant bit (LSB) first 1 SPO – Sampling Polarity 0 = Sample transfer data at the falling edge of clock (SPICLK is '0' when idle) 1 = Sample transfer data at the rising edge of clock (SPICLK is '1' when idle) 0 – – Reserved |
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