TMPR3916 datasheet(39/225 Pages) TOSHIBA

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Chapter 1 The TMPR3916

Preliminary

1-2

1.2

Features

Miscellaneous:

•

60 MHz maximum operating frequency:

•

208 pin QFP package (QFP208-P-2828-0.50)

•

3.3 V power supply voltage

•

ca. 1200mW Maximum Power Dissipation

•

-40°C to 85°C operating ambient temperature

•

Built-in clock generator

•

5V tolerant I/Os on UARTs, TXSEI and CAN-bus interface

•

Unified memory architecture with a high performance dual bus structure (Video bus + CPU bus)

Graphics Display Controller:

•

Four-layer (A-D) overlay hardware processing with transparent color:

•

Layer A, B can display 256 out of 64 K colors each

•

Layer C, D can display 16 out of 64 K colors each

•

Alternatively layer A may be configured in picture mode with 64K colors

•

SDRAM and SRAM frame-buffer memory (SRAM recommended only for low resolutions)

•

Burst access to frame-buffer memory

•

16 bytes built-in dot buffer

•

Built-in color look-up tables (for plane A-D, 544 colors in total)

•

Built-in three-channel 6-bit video DAC, alternatively connection to digital displays (digital RGB

output)

•

Dotclock, horizontal and vertical synchronisation signals can be generated internally or input from

external device

Built-in TX39 Core:

•

Toshiba-developed TX39H core based on MIPS R3000A architecture

•

4 KB Instruction Cache, 1 KB Data Cache

•

Built-in debug support unit for in-system debugging incl. real time PC-tracing

•

Big-endian coding

Peripheral Controllers:

•

Memory Controller (MEMC), 4 channels for SRAM, ROM, Flash

•

SDRAM controller (SDRAMC), 2 channels

•

DMA controller (DMAC), 2 channels

•

Interrupt controller (INTC), 13 internal interrupts, 3 external interrupts, 1 non-maskable interrupt (NMI)

•

Serial I/O : UART 4 channels, TXSEI 1 channel (SPI compatible, with FIFO´s)

•

CAN-bus controller (TXCAN), 2 channels, 16 mailboxes each

•

30 Pin General Purpose I/O´s (PORT)

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