LRI64 datasheet(16/52 Pages) STMICROELECTRONICS

No de pièce	LRI64

Description	Memory TAG IC at 13.56 MHz, with 64-bit Unique ID and WORM user area, ISO15693 and ISO18000-3 Mode 1 compliant

PDF	52 Pages

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Fabricant	STMICROELECTRONICS [STMicroelectronics]

Site Internet	http://www.st.com

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LRI64 to VCD frames

LRI64

16/52

LRI64 to VCD frames

Response Frames are delimited by a Start of Frame (SOF) and an End of Frame (EOF) and

are implemented using a code violation mechanism. The LRI64 supports these in the one

subcarrier mode, at the fast data rate, only.

The VCD is ready to receive a response frame from the LRI64 before 320.9µs (t1) after

having sent a command frame.

9.1

LRI64 SOF

SOF comprises three parts: (see Figure 11)

●

an unmodulated period of 56.64 µs,

●

24 pulses of 423.75 kHz (fc/32),

●

a logic 1 which starts with an unmodulated period of 18.88 µs followed by 8 pulses of

423.75 kHz.

9.2

LRI64 EOF

EOF comprises three parts: (see Figure 12)

●

a logic 0 which starts with 8 pulses of 423.75 kHz followed by an unmodulated period of

18.88 µs.

●

24 pulses of 423.75 kHz (fC/32),

●

an unmodulated time of 56.64 µs.

Figure 11.

Response SOF, using high data rate and one subcarrier

Figure 12.

Response EOF, using high data rate and one subcarrier

AI06671B

113.28 µs

37.76 µs

AI06675B

113.28 µs

37.76 µs

LRI64 Fiches technique(PDF) 16 Page - STMicroelectronics