LRI64 datasheet(13/52 Pages) STMICROELECTRONICS

No de pièce	LRI64

Description	Memory TAG IC at 13.56 MHz, with 64-bit Unique ID and WORM user area, ISO15693 and ISO18000-3 Mode 1 compliant

PDF	52 Pages

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Fabricant	STMICROELECTRONICS [STMicroelectronics]

Site Internet	http://www.st.com

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LRI64

VCD to LRI64 frames

13/52

VCD to LRI64 frames

Request Frames are delimited by a Start of Frame (SOF) and an End of Frame (EOF) and

are implemented using a code violation mechanism. Unused options are reserved for future

use.

The LRI64 is ready to receive a new command frame from the VCD after a delay of t2 (see

Table 14) after having sent a response frame to the VCD.

The LRI64 generates a Power On delay of tPOR (see Table 14) after being activated by the

powering field. After this delay, the LRI64 is ready to receive a command frame from the

VCD.

In ISO 15693 and ISO 18000-3 Mode 1 standards, the SOF is used to define the data

coding mode that the VCD is going to use in the following command frame.

The SOF that is shown in Figure 7 selects the “1-out-of-4” data coding mode. (The LRI64

does not support the SOF for the “1-out-of-256” data coding mode.)

The corresponding EOF sequence is shown in Figure 8.

Figure 7.

Request SOF, using the “1-out-of-4” data coding mode

Figure 8.

Request EOF

AI06660

37.76 µs

9.44 µs

37.76 µs

9.44 µs

AI06662

9.44 µs

37.76 µs

9.44 µs

LRI64 Fiches technique(PDF) 13 Page - STMicroelectronics