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PCAL6408APW Fiches technique(PDF) 40 Page - NXP Semiconductors |
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PCAL6408APW Fiches technique(HTML) 40 Page - NXP Semiconductors |
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40 / 59 page ![]() NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander with interrupt output, reset, and configuration registers 002aag977 DUT CL = 50 pF RL = 1 k SDA VDD(I2C-bus) a. SDA load configuration 002aag981 DUT CL = 50 pF 500 Pn 2 × VDD(P) 500 b. P port load configuration SDA SCL 002aag984 trst trec(rst) tw(rst) RESET Pn START trst ACK or read cycle 0.3 × VDD(I2C-bus) 0.5 × VDD(I2C-bus) 0.5 × VDD(P) trec(rst) CL includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω; tr/tf ≤ 30 ns. The outputs are measured one at a time, with one transition per measurement. I/Os are configured as inputs. All parameters and waveforms are not applicable to all devices. c. RESET timing Figure 35. Reset load circuits and voltage waveforms PCAL6408A All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3.3 — 14 October 2024 Document feedback 40 / 59 |
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