PIC16F690-ESLASHML datasheet(35/294 Pages) MICROCHIP

35 / 294 page

DS41262D-page 33

PIC16F631/677/685/687/689/690

TABLE 2-2:

PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Page

Bank 1

80h

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

xxxx xxxx

44,201

81h

OPTION_REG

RABPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

37,201

82h

PCL

Program Counter’s (PC) Least Significant Byte

0000 0000

44,201

83h

STATUS

IRP

RP1

RP0

ZDC

0001 1xxx

36,201

84h

FSR

Indirect Data Memory Address Pointer

xxxx xxxx

44,201

85h

TRISA

—

TRISA5

TRISA4

TRISA3

TRISA2

TRISA1

TRISA0

--11 1111

59,201

86h

TRISB

TRISB7

TRISB6

TRISB5

TRISB4

—

1111 ----

70,202

87h

TRISC

TRISC7

TRISC6

TRISC5

TRISC4

TRISC3

TRISC2

TRISC1

TRISC0

1111 1111

76,201

88h

—

Unimplemented

—

89h

—

Unimplemented

—

8Ah

PCLATH

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

44,201

8Bh

INTCON

GIE

PEIE

T0IE

INTE

RABIE

T0IF

INTF

RABIF(1)

0000 000x

38,201

8Ch

PIE1

—ADIE(4)

RCIE(2)

TXIE(2)

SSPIE(5)

CCP1IE(3) TMR2IE(3)

TMR1IE

-000 0000

39,202

8Dh

PIE2

OSFIE

C2IE

C1IE

EEIE

—

0000 ----

40,202

8Eh

PCON

—

ULPWUE SBOREN

—

—POR

BOR

--01 --qq

43,202

8Fh

OSCCON

—

IRCF2

IRCF1

IRCF0

OSTS

HTS

LTS

SCS

-110 q000

48,202

90h

OSCTUNE

—

TUN4

TUN3

TUN2

TUN1

TUN0

---0 0000

52,202

91h

—

Unimplemented

—

92h

PR2(3)

Timer2 Period Register

1111 1111

91,202

93h

SSPADD(5, 7)

Synchronous Serial Port (I2C mode) Address Register

0000 0000

184,202

93h

SSPMSK(5, 7)

MSK7

MSK6

MSK5

MSK4

MSK3

MSK2

MSK1

MSK0

1111 1111

187,202

94h

SSPSTAT(5)

SMP

CKE

D/A

R/W

0000 0000

176,202

95h

WPUA(6)

—

—WPUA5

WPUA4

—

WPUA2

WPUA1

WPUA0

--11 -111

62,202

96h

IOCA

—

IOCA5

IOCA4

IOCA3

IOCA2

IOCA1

IOCA0

--00 0000

62,202

97h

WDTCON

—

WDTPS3

WDTPS2

WDTPS1

WDTPS0

SWDTEN

---0 1000

209,202

98h

TXSTA(2)

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

0000 0010

158,202

99h

SPBRG(2)

BRG7

BRG6

BRG5

BRG4

BRG3

BRG2

BRG1

BRG0

0000 0000

161,202

9Ah

SPBRGH(2)

BRG15

BRG14

BRG13

BRG12

BRG11

BRG10

BRG9

BRG8

0000 0000

161,202

9Bh

BAUDCTL(2)

ABDOVF

RCIDL

—

SCKP

BRG16

—

WUE

ABDEN

01-0 0-00

160,202

9Ch

—

Unimplemented

—

9Dh

—

Unimplemented

—

9Eh

ADRESL(4)

A/D Result Register Low Byte

xxxx xxxx

115,202

9Fh

ADCON1(4)

—

ADCS2

ADCS1

ADCS0

—

-000 ----

114,202

Legend:

– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

Note

MCLR and WDT Reset do not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the

mismatch exists.

PIC16F687/PIC16F689/PIC16F690 only.

PIC16F685/PIC16F690 only.

PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.

PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.

RA3 pull-up is enabled when pin is configured as MCLR in Configuration Word.

Accessible only when SSPCON register bits SSPM<3:0> = 1001.

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