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MCP3909 Fiches technique(PDF) 13 Page - Microchip Technology

No de pièce MCP3909
Description  Energy Metering IC with SPI Interface and Active Power Pulse Output
PDF  40 Pages
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Fabricant  MICROCHIP [Microchip Technology]
Site Internet  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP3909 Fiches technique(HTML) 13 Page - Microchip Technology

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© 2006 Microchip Technology Inc.
DS22025A-page 13
MCP3909
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
3.1
Digital VDD (DVDD)
DVDD is the power supply pin for the digital circuitry
within the MCP3909.
This pin requires appropriate bypass capacitors and
should be maintained to 5V ±10% for specified
operation.
Refer
to
Section 6.0
“Applications
Information”.
3.2
High-Pass Filter Input Logic Pin
(HPF)
HPF controls the state of the high-pass filter in both
input channels. A logic ‘1’ enables both filters,
removing any DC offset coming from the system or the
device. A logic ‘0’ disables both filters allowing DC
voltages to be measured.
3.3
Analog VDD (AVDD)
AVDD is the power supply pin for the analog circuitry
within the MCP3909.
This pin requires appropriate bypass capacitors and
should be maintained to 5V ±10% for specified
operation.
Refer
to
Section 6.0
“Applications
Information”.
3.4
Current Channel (CH0-, CH0+)
CH0- and CH0+ are the fully differential analog voltage
input
channels
for
the
current
measurement,
containing a PGA for small-signal input, such as shunt
current sensing. The linear and specified region of this
channel is dependant on the PGA gain. This
corresponds to a maximum differential voltage of
±470 mV/G and maximum absolute voltage, with
respect to AGND, of ±1V. Up to ±6V can be applied to
these pins without the risk of permanent damage.
Refer to Section 1.0 “Electrical Characteristics”.
Pin No.
Symbol
Function
1DVDD
Digital Power Supply Pin
2
HPF
High-Pass Filters Control Logic Pin
3AVDD
Analog Power Supply Pin
4
NC
No Connect
5
CH0+
Non-Inverting Analog Input Pin for Channel 0 (Current Channel)
6
CH0-
Inverting Analog Input Pin for Channel 0 (Current Channel)
7
CH1-
Inverting Analog Input Pin for Channel 1 (Voltage Channel)
8
CH1+
Non-Inverting Analog Input Pin for Channel 1 (Voltage Channel)
9MCLR
Master Clear Logic Input Pin
10
REFIN/OUT
Voltage Reference Input/Output Pin
11
AGND
Analog Ground Pin, Return Path for internal analog circuitry
12
SCK / F2
Serial Clock or Frequency Control for HFOUT Logic Input Pin
13
SDI / F1
Serial Data Input or Frequency Control for FOUT0/1 Logic Input Pin
14
CS / F0
Chip Select or Frequency Control for FOUT0/1 Logic Input Pin
15
G1
Gain Control Logic Input Pin
16
G0
Gain Control Logic Input Pin
17
OSC1
Oscillator Crystal Connection Pin or Clock Input Pin
18
OSC2
Oscillator Crystal Connection Pin or Clock Output Pin
19
NC
No Connect
20
SDO / NEG
Serial Data Out or Negative Power Logic Output Pin
21
DGND
Digital Ground Pin, Return Path for Internal Digital Circuitry
22
HFOUT
High-Frequency Logic Output Pin (Intended for Calibration)
23
FOUT1
Differential Mechanical Counter Logic Output Pin
24
FOUT0
Differential Mechanical Counter Logic Output Pin



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