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MF1ICS2005 Fiches technique(PDF) 4 Page - NXP Semiconductors

No de pièce MF1ICS2005
Description  Sawn bumped 120關m wafer addendum
PDF  7 Pages
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Fabricant  NXP [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo NXP - NXP Semiconductors

MF1ICS2005 Fiches technique(HTML) 4 Page - NXP Semiconductors

  MF1ICS2005 Datasheet HTML 1Page - NXP Semiconductors MF1ICS2005 Datasheet HTML 2Page - NXP Semiconductors MF1ICS2005 Datasheet HTML 3Page - NXP Semiconductors MF1ICS2005 Datasheet HTML 4Page - NXP Semiconductors MF1ICS2005 Datasheet HTML 5Page - NXP Semiconductors MF1ICS2005 Datasheet HTML 6Page - NXP Semiconductors MF1ICS2005 Datasheet HTML 7Page - NXP Semiconductors  
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© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 3.0 — 18 July 2007
4 of 7
NXP Semiconductors
MF1 IC S20 05
Sawn bumped 120µm wafer addendum
6.
Chip orientation and bond pad locations
Fig 1.
Chip orientation and bond pad locations
PAD (center) x [µm]
y [µm]
VSS
0.0
0.0
TESTIO
252.2
602.3
LA
17.4
596.1
LB
712.4
0.0
(1) X - Scribeline width:
80 µm
106.5 µm
(2) Y- Scribeline width:
80 µm
103.0 µm
(3) Chip step, x -length:
1.11 mm
133.4 µm
(4) Chip step, y -length:
1.06 mm
(8) LB bump edge to chip edge, x-length:
88.6 µm
(1)
X
Y
LA
TESTIO
VSS
LB
MF1ICS2005
(4)
(3)
(5)
(6)
(2)
(7)
(8)
(6) LA bump edge to chip edge, x-length:
(7) LB bump edge to chip edge, y-length:
(5) LA bump edge to chip edge, y-length:



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