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SC2000 Fiches technique(PDF) 33 Page - NXP Semiconductors

No de pièce SC2000
Description  Universal Timeslot Interchange
PDF  44 Pages
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Fabricant  PHILIPS [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

SC2000 Fiches technique(HTML) 33 Page - NXP Semiconductors

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2000 Sep 07
33
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Figure 11. CLK_IN, SYNC_IN — SCbus Mode (CLK_IN Divider = 2)
Table 11. CLK_IN, SYNC_IN — SCbus Mode (CLK_IN Divider = 2)
Symbol
Parameter
Min
Typ
Max
Unit
t1
CLK_IN period
244
ns
t2
CLK_IN high time
122
ns
t3
CLK_IN low time
122
ns
t4
SYNC_IN low setup to CLK_IN
↓(PEB conventional)
10
ns
t5
SYNC_IN low hold from CLK_IN
↓(PEB conventional)
10
ns
t6
SYNC_IN high setup to CLK_IN
↓(PEB conventional)
10
ns
t7
SYNC_IN high hold from CLK_IN
↓(PEB conventional)
10
ns
t8
SYNC_IN setup to CLK_IN
↓(ST-BUS)
10
ns
t9
SYNC_IN hold from CLK_IN
↓ (ST-BUS)
10
ns
t10a
SCLKx2*
↓delay from CLK_IN↑ (PEB conventional)
25
ns
t10b
SCLKx2*
↓delay from CLK_IN↓ (ST-BUS)
25
ns
t11a
SCLKx2*
↑delay from CLK_IN↓(PEB conventional)
25
ns
t11b
SCLKx2*
↑delay from CLK_IN↑(ST-BUS)
25
ns
t12a
SCLK
↑ delay from CLK_IN↑(PEB conventional)
25
ns
t12b
SCLK
↑ delay from CLK_IN↓(ST-BUS)
25
ns
t13a
SCLK
↓ delay from CLK_IN↑(PEB conventional)
25
ns
t13b
SCLK
↓delay from CLK_IN↓ (ST-BUS)
25
ns
t14
FSYNC*
↓ delay from SCLKx2*↑
30
ns
t15
FSYNC*
↑ delay from SCLKx2*↑
30
ns
Note:
1. Timing measured with 200 pF load on all SCbus outputs.
t1
t2
t3
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10a
t10b
t11a
t11b
t12a
t12b
t13a
t13b
t14
t15
CLK_IN (Conventional)
SYNC_IN (Conventional)
CLK_IN (ST-BUS)
SYNC_IN (ST-BUS)
SCLKX2*
SCLK
FSYNC*



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