STLD20D-DEF datasheet(23/31 Pages) STMICROELECTRONICS

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STLD20D

Layout recommendation

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Layout recommendation

The package connection of the STLD20D has been realized in order to facilitate the layout

of the PCB. The golden rule to obtain an optimized layout is to split the power and signal track

as shown on the

Figure 24.

It is necessary to place the input capacitor as closed as possible between pin1 and pin2 of

the STLD20D package. If the CIN capacitor is not closed to the device, high frequency noise

due to gate driver dI/dt flows through the copper track of the board and can generate some

line voltage drop due to the line inductance.

For the same reason, in order to eliminate high frequency current loop, the connection of the

diode (D) and the output capacitor (COUT) must be as close as possible to the internal power

MosFET (SW) (close to pin 8 and 1).

Concerning the signal path, we recommend to create the PCB GND signal from the pin 1

("A" point in the

Figure 24.). Thus all signal references such as feedback and the voltage

across Rset are not disturbed by the power stage.

Figure 24.

Layout suggested

GND

VIN

COUT

STLD20D

CIN

RSET

SHDN

RLED

STLD20D-DEF Fiches technique(PDF) 23 Page - STMicroelectronics