PCK857 datasheet(2/8 Pages) PHILIPS

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Philips Semiconductors

Preliminary specification

PCK857

66–150MHz Phase Locked Loop Differential 1:10

SDRAM Clock Driver

1998 Dec 10

FEATURES

• Optimized for clock distribution in DDR (Double Data Rate)

SDRAM applications

• 1-to-10 differential clock distribution

• Very low skew (< 100ps) and jitter (< 100ps)

• 3V AV

CC and 2.5V Vddq

• SSTL_2 interface clock inputs and outputs

• CMOS control signal input

• Test mode enables buffers while disabling PLL

• Low current power-down mode

• Tolerant of Spread Spectrum input clock

• Full DDR solution provided when used with SSTL16857 and

CBT3857

DESCRIPTION

Zero delay buffer to distribute an SSTL differential clock input pair to

10 SSTL_2 differential output pairs. Outputs are slope controlled.

External feedback pin for synchronization of the outputs to the input.

A CMOS style Enable/Disable pin is provided for low power disable.

PIN CONFIGURATION

GND

VDDQ

GND

VDDQ

CLK

VDDQ

AVCC

AGND

GND

VDDQ

GND

VDDQ

GND

VDDQ

FBIN

VDDQ

FBOUT

GND

VDDQ

SW00358

GND

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

OUTSIDE NORTH AMERICA

NORTH AMERICA

DRAWING NUMBER

48-Pin Plastic TSSOP

°C to +70°C

PCK857 DGG

SOT362-1

PINS

SYMBOL

DESCRIPTION

1, 7, 8, 18, 24, 25, 31, 41, 42, 48

GND

SSTL_2 ground pins

2, 3, 5, 6, 9, 10, 19, 20, 22, 23, 26, 27, 29,

30, 32, 33, 39, 40, 43, 44, 46, 47

Yn, Ynb, FBOUT, FBOUTb

SSTL_2 differential outputs

4, 11, 12, 15, 21, 28, 34

VDDQ

SSTL_2 power pins

13, 14, 35, 36

CLKIN, CLKINb, FBIN, FBINb

SSTL_2 differential inputs

AVCC

Analog power

AGND

Analog ground

Power-down control input

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