DESCRIPTION
Zero delay buffer to distribute an SSTL differential clock input pair to 10 SSTL_2 differential output pairs. Outputs are slope controlled.
External feedback pin for synchronization of the outputs to the input.
A CMOS style Enable/Disable pin is provided for low power disable.

FEATURES
• Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications
• 1-to-10 differential clock distribution
• Very low skew (< 100ps) and jitter (< 100ps)
• 3V AVCC and 2.5V Vddq
• SSTL_2 interface clock inputs and outputs
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Full DDR solution provided when used with SSTL16857 and CBT3857