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WM8775SEDS/R Fiches technique(PDF) 22 Page - Wolfson Microelectronics plc |
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WM8775SEDS/R Fiches technique(HTML) 22 Page - Wolfson Microelectronics plc |
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22 / 39 page ![]() WM8775 Production Data w PD Rev 4.1, June 2006 22 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION In left/right/ I 2S modes: ADCLRC Polarity (normal) 0 : normal ADCLRC polarity 1: inverted ADCLRC polarity R11(0Bh) 0001011 Interface Control 2 ADCLRP 0 In DSP mode: 0 : DSP mode A 1: DSP mode B By default, ADCLRC is sampled on the rising edge of BCLK and should ideally change on the falling edge. Data sources that change ADCLRC on the rising edge of BCLK can be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCLK to the inverse of that shown in Figures 12, 13, 14, and 15. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R11(0Bh) 0001011 Interface Control 3 ADCBCP 0 BCLK Polarity (DSP modes) 0 : normal BCLK polarity 1: inverted BCLK polarity The WL[1:0] bits are used to control the input word length. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R11(0Bh) 0001011 Interface Control 5:4 ADCWL [1:0] 10 Word Length 00 : 16 bit data 01: 20 bit data 10: 24 bit data 11: 32 bit data Note: 1. If 32-bit mode is selected in right justified mode, the WM8775 defaults to 24 bits. 2. In 24 bit I 2S mode, any width of 24 bits or less is supported provided that ADCLRC is high for a minimum of 24 BCLKs and low for a minimum of 24 BCLKs. When operating the ADC digital interface in slave mode, to optimise the performance of the ADC it is recommended that the ADCMCLK and ADCBCLK input signals do not have coinciding rising edges. The ADCMCLK bit provides the option to internally invert the ADCMCLK input signal when the input signals have coinciding rising edges. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R11(0Bh) 0001011 Interface Control 6 ADCMCLK 0 ADCMCLK Polarity 0 : non-inverted 1: inverted ADC MASTER MODE Control bit MS selects between audio interface Master and Slave Modes. In Master mode ADCLRC and BCLK are outputs and are generated by the WM8775. In Slave mode ADCLRC and BCLK are inputs to WM8775. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R12(0Ch) 0001100 Interface Control 8 ADCMS 0 Audio Interface Master/Slave Mode select: 0 : Slave Mode 1: Master Mode |
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