WM8775SEDSSLASHR datasheet(33/39 Pages) WOLFSON

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Production Data

WM8775

PD Rev 4.1, June 2006

7:0

LAG[7:0]

11001111

(0dB)

Attenuation data for left channel ADC gain in 0.5dB steps

R14 (0Eh)

0001110

Attenuation

ADCL

ZCLA

Left channel ADC zero cross enable:

0: Zero cross disabled

1: Zero cross enabled

7:0

RAG[7:0]

11001111

(0dB)

Attenuation data for right channel ADC gain in 0.5dB steps

R15 (0Fh)

0001111

Attenuation

ADCR

ZCRA

Right channel ADC zero cross enable:

0: Zero cross disabled

1: Zero cross enabled

3:0

LCT[3:0]

1011

(-5dB)

Limiter Threshold/ALC target level in 1dB steps.

0000: -16dB FS

0001: -15dB FS

…

1101: -3dB FS

1110: -2dB FS

1111: -1dB FS

6:4

MAXGAIN[2:0]

111 (+24dB)

Set Maximum Gain of PGA

111 : +24dB

110 : +20dB

….(-4dB steps)

010 : +4dB

001 : 0dB

000 : 0dB

R16 (10h)

0010000

ALC Control 1

8:7

LCSEL[1:0]

ALC/Limiter function select

00 = Limiter

01 = ALC Right channel only

10 = ALC Left channel only

11 = ALC Stereo (PGA registers unused)

3:0

HLD[3:0]

0000

(0ms)

ALC hold time before gain is increased.

0000: 0ms

0001: 2.67ms

0010: 5.33ms

… (time doubles with every step)

1111: 43.691s

ALCZC

0 (zero

cross off)

ALC uses zero cross detection circuit.

R17 (11h)

0010001

ALC Control 2

LCEN

Enable Gain control circuit.

0 = Disable

1 = Enable

ALC/Limiter attack (gain ramp-down) time

3:0

ATK[3:0]

0010

(24ms)

ALC mode

0000: 8.4ms

0001: 16.8ms

0010: 33.6ms…

(time doubles with every step)

1010 or higher: 8.6s

Limiter Mode

0000: 250us

0001: 500us…

0010: 1ms

(time doubles with every step)

1010 or higher: 256ms

ALC/Limiter decay (gain ramp up) time

R18 (12h)

0010010

ALC Control 3

7:4

DCY[3:0]

0011

(268ms/

9.6ms)

ALC mode

0000: 33.5ms

0001: 67.2ms

0010: 134.4ms ….(time

doubles for every step)

1010 or higher: 34.3ms

Limiter mode

0000: 1.2ms

0001: 2.4ms

0010: 4.8ms ….(time doubles

for every step)

1010 or higher: 1.2288s

WM8775SEDS/R Fiches technique(PDF) 33 Page - Wolfson Microelectronics plc

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