STE10A datasheet(19/82 Pages) STMICROELECTRONICS

No de pièce	STE10A

Description	PCI 10/100 Ethernet controller with integrated PHY (3.3V)

PDF	82 Pages

Scroll/Zoom	100%

Fabricant	STMICROELECTRONICS [STMicroelectronics]

Site Internet	http://www.st.com

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19 / 82 page

STE10/100A

Functional description

19/82

3.4

Receive scheme and receive early interrupt scheme

The following figure shows the difference of timing without early interrupt and with early

interrupt.

Figure 12.

Receive data flow (without early interrupt and with early interrupt)

Figure 13.

Detailed receive early interrupt flow

Incoming packet

Receive FIFO operation

FIFO-to-host memory operation

Interrupt

Driver read header

Higher layer process

Driver read the rest data

Receive early interrupt

Higher layer process (early)

Time

: without early interrupt

: with early interrupt

Driver read the rest data

Finish time

Driver read header (early)

PC00357

FIFO-to-host memory operation

Receive early interrupt

Driver read header (early)

Higher layer process (early)

Driver read the rest data

Finish

1st

descriptor

full

2descriptor

The size of 1st

descriptor is

programmed as the

header size in

advance

Issue 2

interrupt at end

of packet

Time

PC00358

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