80221 datasheet(32/91 Pages) LSI

32 / 91 page

80220/80221

MD400159/E

Table 8. MI Serial Port Frame Structure

<Idle>

<Start>

<Read>

<Write>

<Reg. Addr.>

<Data>

IDLE

ST[1:0]

READ

WRITE

PHYAD[4:0]

REGAD[4:0]

TA[1:0]

D[15:0]....

Control

Status

PHY ID #1

PHY ID #2

AutoNegotiation Advertisement

AutoNegotiation Remote End Capability

Configuration 1

Configuration 2

Status Output

Mask

Reserved

Symbol

Name

Definition

R/W

IDLE

Idle Pattern

These bits are an idle pattern. Device will not initiate an

MI cycle until it detects at least 32 1's.

ST1

Start Bits

When ST[1:0]=01, a MI Serial Port access cycle starts.

ST0

READ

Read Select

1 = Read Cycle

WRITE

Write Select

1 = Write Cycle

PHYAD[4:0]

Physical Device

When PHYAD[4:0]=MDA[4:0] pins inverted, the MI Serial

Address

Port is selected for operation.

REGAD4[4:0]

If REGAD[4:0]=00000-11110, these bits determine the

specific register from which D[15:0] is read/written. If multiple

registers are read/written in a single cycle.

TA1

Turnaround Time

These bits provide some turnaround time for MDIO

R/W

TA0

When READ=1, TA[1:0]=Z0

When WRITE=1, TA[1:0]=ZZ

D[15:0]....

Data

These 16 bits contain data to/from one of the eleven registers

Any

selected by register address bits REGAD[4:0].

IDLE is shifted in first

4.0 Register Description

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