CS53L21 datasheet(16/66 Pages) CIRRUS

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DS700PP1

CS53L21

SWITCHING SPECIFICATIONS - I²C CONTROL PORT

(Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL =30pF)

11. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

Parameter

Symbol

Min

Max

Unit

SCL Clock Frequency

fscl

100

kHz

RESET Rising Edge to Start

tirs

500

Bus Free Time Between Transmissions

tbuf

4.7

µs

Start Condition Hold Time (prior to first clock pulse)

thdst

4.0

µs

Clock Low time

tlow

4.7

µs

Clock High Time

thigh

4.0

µs

Setup Time for Repeated Start Condition

tsust

4.7

µs

SDA Hold Time from SCL Falling

(Note 11)

thdd

µs

SDA Setup time to SCL Rising

tsud

250

Rise Time of SCL and SDA

trc

-1

µs

Fall Time SCL and SDA

tfc

300

Setup Time for Stop Condition

tsusp

4.7

µs

Acknowledge Delay from SCL Falling

tack

300

3450

t buf

t hdst

low

t r

t f

hdd

t high

t sud

t sust

t susp

Stop

Start

Stop

Repeated

SDA

SCL

t irs

RST

Figure 5. Control Port Timing - I²C

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