MC68340 datasheet(85/441 Pages) FREESCALE

No de pièce	MC68340

Description	Integrated Processor with DMA User?셲 Manual

PDF	441 Pages

Scroll/Zoom	100%

Fabricant	FREESCALE [Freescale Semiconductor, Inc]

Site Internet	http://www.freescale.com

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MC68340 USER’S MANUAL

MOTOROLA

INTERNAL

PROCESSING

STACK

WRITE

CYCLE

CLKOUT

DSACKx

R/W

BERR

FC3–FC0

D15–D0

A31–A0

Figure 3-18. Late Bus Error with

DSACK

≈

3.5.2 Retry Operation

When both

BERR and HALT are asserted by an external device during a bus cycle, the

MC68340 enters the retry sequence shown in Figure 3-19. A delayed retry, which is

similar to the delayed

BERR signal described previously, can also occur (see Figure 3-20).

The MC68340 terminates the bus cycle, places the control signals in their inactive state,

and does not begin another bus cycle until the

BERR and HALT signals are negated by

external logic. After a synchronization delay, the MC68340 retries the previous cycle using

the same access information (address, function code, size, etc.).

BERR should be negated

before S2 of the retried cycle to ensure correct operation of the retried cycle.

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MC68340 Fiches technique(PDF) 85 Page - Freescale Semiconductor, Inc