10
MPC89E58A Technical Summary
MEGAWIN
Nonvolatile Registers:
There are two Nonvolatile Registers named OR0 and OR1 individually. They are designed to
configure the MPC89E58A options.
Generally these two nonvolatile registers will be written via a popular NVM writer, say Hi-Lo
System All-11, Leaper-48 and Megawin-Provided MCU writer. Furthermore, the user can
change the NVM register OR1 by his ISP program in a manner as same as he does in writing
the data flash, but OR0 can be written only via an off-line popular NVM writer.
NVM register: OR0 (Option Register 0):
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
-
-
ISPAS1
ISPAS0
-
MOVCL
SB
LOCK
{ISPAS1, ISPAS0}: Used to identify the start address for ISP program
{0, 0}: = The ISP space is from 0xEC00 to 0xFBFF (4K size).
{0, 1}: = The ISP space is from 0xF400 to 0xFBFF (2K size).
{1, 0}: = The ISP space is from 0xF800 to 0xFBFF (1K size)
{1, 1}: = No ISP space.
These two bits decide where the ISP program locates, and how the ISP program and the data flash
shares the 31K embedded flash.
MOVCL:
Used to decide if MOVC instruction will be disabled.
0 :=
MOVC is conditionally disabled.
1 := MOVC is always available.
SB:
Used to decide if the program code will be scrambled while it is dumped.
0 := Code dump from Writer is scrambled.
1 := Code dump from Writer is transparent.
LOCK:
Used to decide if the program code will be locked against the popular writer.
0 := lock code.
1 := does not lock code
If the code is locked, all the data dumped from a popular will always show FFh.
The default value of the OR0 is FFh.
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