IDTTM

Frequency Generator and Integrated Buffers for Celeron & PII/IIITM

0395F—01/25/10

ICS9250-27

Frequency Generator and Integrated Buffers for Celeron & PII/IIITM

4

2

S

F1

S

F0

S

FU

P

CM

A

R

D

S6

6

V

3I

C

Pz

H

M

8

4F

E

RC

I

P

A

O

I

X0

0

e

t

a

t

s

i

r

Te

t

a

t

s

i

r

Te

t

a

t

s

i

r

Te

t

a

t

s

i

r

Te

t

a

t

s

i

r

Te

t

a

t

s

i

r

Te

t

a

t

s

i

r

T

X0

1

2

/

K

L

C

T2

/

K

L

C

T3

/

K

L

C

T6

/

K

L

C

T2

/

K

L

C

TK

L

C

T6

/

K

L

C

T

01

0

z

H

M

6

.

6

6z

H

M

0

0

1

6

.

6

6

z

H

M

z

H

M

3

.

3

3z

H

M

8

4

8

1

3

.

4

1

z

H

M

3

.

3

3

z

H

M

01

1

z

H

M

0

0

1z

H

M

0

0

1

6

.

6

6

z

H

M

z

H

M

3

.

3

3z

H

M

8

4

8

1

3

.

4

1

z

H

M

3

.

3

3

z

H

M

11

0

z

H

M

3

3

1z

H

M

3

3

1

6

.

6

6

z

H

M

z

H

M

3

.

3

3z

H

M

8

4

8

1

3

.

4

1

z

H

M

3

.

3

3

z

H

M

111

z

H

M

3

3

1z

H

M

0

0

1

6

.

6

6

z

H

M

z

H

M

3

.

3

3z

H

M

8

4

8

1

3

.

4

1

z

H

M

3

.

3

3

z

H

M

Truth Table

Byte 0: Control Register

(1 = enable, 0 = disable)

t

i

B#

n

i

Pe

m

a

ND

W

Pn

o

i

t

p

i

r

c

s

e

D

7

t

i

BD

I

d

e

v

r

e

s

e

R0

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

6

t

i

BD

I

d

e

v

r

e

s

e

R0

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

5

t

i

BD

I

d

e

v

r

e

s

e

R0

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

4

t

i

BD

I

d

e

v

r

e

s

e

R0

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

3

t

i

B

m

u

r

t

c

e

p

S

d

a

e

r

p

S

)

f

f

O

=

0

/

n

O

=

1

(

1)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

2

t

i

B6

21

z

H

M

8

41

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

1

t

i

B5

20

z

H

M

8

41

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

0

t

i

B9

42

K

L

C

U

P

C1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

Note: Reserved ID bits must be wirtten as "0".

Byte 1: Control Register

(1 = enable, 0 = disable)

t

i

B#

n

i

Pe

m

a

ND

W

Pn

o

i

t

p

i

r

c

s

e

D

7

t

i

B6

37

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

6

t

i

B7

36

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

5

t

i

B9

35

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

4

t

i

B0

44

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

3

t

i

B2

43

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

2

t

i

B3

42

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

1

t

i

B5

41

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

0

t

i

B6

40

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

Notes:

1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be

configured at power-on and are not expected to be configured during the normal modes of operation.

2. PWD = Power on Default