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AM29PDL129H Fiches technique(PDF) 41 Page - SPANSION

No de pièce AM29PDL129H
Description  128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control and Dual chip Enable
PDF  49 Pages
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Fabricant  SPANSION [SPANSION]
Site Internet  http://www.spansion.com
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AM29PDL129H Fiches technique(HTML) 41 Page - SPANSION

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November 2, 2005
Am29PDL129H
39
AC CHARACTERISTICS
OE#
CE1# or CE2#
WE#
Addresses
tOH
Data
Valid
In
Valid
In
Valid PA
Valid RA
tWC
tWPH
tAH
tWP
tDS
tDH
tAS
tRC
tCE
tAH
Valid
Out
tOE
tACC
tOEH
tGHWL
tDF
Valid
In
CE# Controlled Write Cycles
WE# Controlled Write Cycle
Valid PA
Valid PA
tCP
tCPH
tWC
tWC
Read Cycle
tSR/W
tAS
Note:
1. During CE1# transitions, CE2#= VIH; During CE2# transitions, CE1#= VIH
Figure 17.
Back-to-back Read/Write Cycle Timings
WE#
CE1# or CE2#
OE#
High Z
tOE
High Z
DQ7
DQ6–DQ0
RY/BY#
tBUSY
Complement
True
Addresses
VA
tOEH
tCE
tCH
tOH
tDF
VA
VA
Status Data
Complement
Status Data
True
Valid Data
Valid Data
tACC
tRC
Note:
1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read
cycle. During CE1# transitions, CE2#= VIH;
2. During CE2# transitions, CE1#= VIH
Figure 18.
Data# Polling Timings (During Embedded Algorithms)



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