ADIS16201SLASHPCB datasheet(25/32 Pages) AD

25 / 32 page

Data Sheet

ADIS16201

Rev. C | Page 25 of 32

Once the ADIS16201 is placed into the power-down mode, it

can only return to normal operation by timing out, a reset

command (using the RST hardware control line), or by cycling

the power applied to the part. Once awake, the seven data

output registers can be scanned to determine what the state of

the output registers were prior to powering down. Once the

data is recovered, the device can be powered down again by

writing a non-zero value to the PWR_MDE control register and

starting the process over.

Once the power-down time is complete, the recovery time for

the ADIS16201 is approximately 2 ms. This recovery time is

implemented within the device to allow for recovery of the ADC

prior to performing the next data conversion. Note that the ND

data bit within the seven data output control registers is cleared

when the ADIS16201 is powered down. Likewise, the new data

hardware I/O line is placed into an inactive state prior to being

powered down. The DAC is placed into a power-down mode as

well, which results in the DAC output dropping to 0 V during

the power-down period. All control register settings are retained

while powered down with the exception of the PWR_MDE

control register, which is reset to 0 prior to power-down.

PWR_MDE Register Definition

Address

Default1

Format

Access

0x3B, 0x3A

0x0000

Binary

R/W

Default is valid only until the first register write cycle.

The power-down period is determined by multiplying the

binary value represented by the data bits times the constant

0.5 seconds. This results in a variable power-down period of

0.5 seconds to 127.5 seconds with 0.5 seconds resolution in the

setting. A setting of 0 disables the power-down mode, whereas

any non-zero entry places the device in the power-down mode

at the next update of the data output registers. The power-down

recovery from the power-down mode.

Table 26. PWR_MDE Bit Descriptions

Bit

Description

15:8

Not used

7:0

Data bits

STATUS FEEDBACK

The status control register within the ADIS16201 is utilized in

determining the present state of the device. The ability to monitor

the device becomes necessary when and if the ADIS16201 has

registered an alarm or error condition as indicated by the “alarm

enable” (14) within the seven output data registers. The 16-bit

status register is broken into two bytes. The three lower bits of the

lower data byte are used to indicate which error condition exists,

while the two lower bits of the upper data byte are utilized in

indicating which alarm condition exists.

STATUS Register Definition

Address

Default1

Format

Access

0x3D, 0x3C

0x0000

N/A

Read only

Default is valid only until the first register write cycle.

The STATUS control register contains the alarm/error flags that

indicate abnormal operating conditions. See Table 27 for each

status bit definition. All flags are cleared upon the reading of the

status register. The flags are set on a continuing basis as long as

the error or alarm conditions persist.

Table 27. STATUS Bit Descriptions

Bit

Description

15:10

Not used.

Alarm 2 status.

1: Active

0: Normal mode

Alarm 1 status.

1: Active

0: Normal mode

7:4

Not used.

SPI communications failure.

1: Error condition

0: Normal mode

Control register update failed.

1: Error condition

0: Normal mode

Power supply above 3.625 V.

1: Error condition

0: Normal mode

Power supply below 2.975 V.

1: Error condition

0: Normal mode

COMMAND CONTROL

The COMMAND control register is utilized in sending global

commands to the ADIS16201 device. There are four separate

commands that act as global commands in the controlling of

the ADIS16201 operation. Any one of the four commands can

be implemented by writing 1 to its corresponding bit location.

The command control register has write-only capability and is

volatile.

Table 28 describes each of these global commands.

COMMAND Register Definition

Address

Default1

Format

Access

0x3F, 0x3E

0x0000

N/A

Write only

Default is valid only until the first register write cycle.

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