ADIS16201SLASHPCB datasheet(17/32 Pages) AD

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Data Sheet

ADIS16201

Rev. C | Page 17 of 32

PROGRAMMING AND CONTROL

CONTROL REGISTER OVERVIEW

The ADIS16201 offers many programmable features that are

controlled by writing commands to the appropriate control

registers using the SPI. For added system flexibility and

programmability, the following sections describe these controls

and specify the 28 digital control registers that are available

using the SPI interface. A high level listing of these registers is

given within Table 9. The following sections expand upon the

functionality of each of these control registers, providing for the

full clarification of the behavior of each of the control registers.

Available control modes for the device include selectable sample

rates for reading the seven output vectors, configurable output

data, alarm settings, control of the on-board 12-bit auxiliary

DAC, handling of the two general-purpose I/O lines, facilitation

of the sleep mode, enabling the self-test mode, and other

miscellaneous control functions.

The conversion process is repeated continually, providing for

continuous update of the seven output registers. The new data

ready bit (ND) flags bits common to all seven output registers,

allowing the completion of the conversion process to be tracked

via the SPI. As an alternative, the digital I/O lines can be configured

through software control to create a data-ready hardware function

that can signal the completion of the conversion process.

Two independent alarms provide the ability to monitor any one

of the seven output registers. They can be configured to report

an alarm condition on either fixed thresholds or rates of change.

The alarm conditions are monitored through the SPI. In addition,

the user can configure the digital I/O lines through software

control to create an alarm function that allows for monitoring

of the alarm conditions through hardware.

The seven output signals noted above are calibrated independ-

ently at the factory, delivering a high degree of accuracy. In

addition, the user has access to independent offset and scale

factors for each of the two acceleration and inclination output

vectors. This allows independent scaling and level adjustment

control of any one these four registers prior to the values being

read via the SPI. In turn, field level calibrations can be implemented

within the sensor itself using these offset and scale variables.

System level commands provided within the sensor include

automatic zeroing of the four outputs using a single null command

via the SPI. In addition, the original factory calibration settings

can be recovered at any point, using a simple factory reset

command.

CONTROL REGISTER ACCESS

The control registers within the ADIS16201 are based upon a

16-bit/2-byte format, and they are accessed via the SPI. The SPI

operates in full duplex mode with the data clocked out of the

DOUT pin at the same time data is clocked in through the DIN

pin. All commands written to the ASIS16201 are categorized as

write commands or read commands. All write commands are

self-contained and take place within a single cycle. Each read

command requires two cycles to complete; the first cycle is for

transmitting the register address, and the second cycle is for

reading the data. During the second cycle, when the data out

line is active, the data in line is used to receive the next

sequential command. This allows for overlapping the commands.

For more information on basic SPI port operation, see the

Applications section.

The read and write commands are identified through the most

significant bit (MSB), B15, of the received data. Write a 1 to B15

to indicate a write command. Write a 0 to B15 to indicate a read

command. Bit B13 through Bit B8 contain the address of the

control register that is being accessed. The remaining eight bits of

the write command contain the data that is being written into the

part, whereas the remaining eight bits of the read command

contain don’t care levels. Given that the data within the write

command is eight bits in length, the 8-bit data format is the

default byte size. A write command operates on a single chip

select cycle, as shown in Figure 35. The read command operates

on a 2-chip select cycle basis, as seen in Figure 34. All 64 bytes of

into the device is one byte at a time with the address of each byte

being explicitly called out in the write command. Conversely, data

being read from the device consists of two, back-to-back, 8-bit

variables being sent out, with the first byte out corresponding to

the upper address (odd number address) and the second byte

relating to the next lower address space (even number address).

For example, a data read of Address 03h results in the data from

Address 03h being fed out followed by data from Address 02h.

Likewise, a data read of Address 02h results in the same data

stream being output from the device.

The ADIS16201 is a flash-based device with the nonvolatile

functional registers implemented as flash registers. Take into

account the endurance limitation of 20,000 writes when

considering the system-level integration of these devices. The

nonvolatile column in Table 9 indicates which registers are

recovered upon power-up. The user must instigate a manual

flash update command (using the command register) in order

to store the nonvolatile data registers, once they are configured

properly. When performing a manual flash update command,

the user needs to ensure that the power supply remains within

limits for a minimum of 50 μs after the write is initiated. This

ensures a successful write of the nonvolatile data.

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